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肛交 准备 西电闇练个东谈主主页系统 李祥东 汉文主页

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肛交 准备 西电闇练个东谈主主页系统 李祥东 汉文主页
发布日期:2024-12-05 05:12    点击次数:84

肛交 准备 西电闇练个东谈主主页系统 李祥东    汉文主页

李祥东博士,江苏东谈主,西安电子科技大学广州商榷院华山学者菁英陶冶,硕士生导师,广州第三代半导体编削中心副主任,辩认于2013年和2016年获西安电子科技大学微电子学士学位和硕士学位,2020年获比利时鲁汶大学(KU Leuven)欧洲微电子中心IMEC博士学位,领有超 10 年的第三代半导体 GaN 芯片研发告诫,先后师从第三代半导体领域着名巨匠张进成陶冶和 IEEE Fellow、IMEC Fellow、charge pumping 测量本事发明东谈主 Guido Groeseneken 陶冶。深度参与了 imec 各人首家商用级 8 英寸硅基氮化镓本事体系的成立。

接待报考2023级硕士商榷生~

所获荣誉:

1)欧洲微电子中心imec 2020年度“不凡博士奖”(3个限额/400+博士);

2)2020年度"外洋优秀私费留学生"奖学金;

3)西安电子科技大学“硕士优秀毕业论文格外奖”(top3/2000+硕士);

4)2010、2011、2015年度国度奖学金.

科研神志:

2021.12~2025.11: 国度要点研发规画“面向大数据中心欺诈的 8 英寸硅衬底上氮化镓基外延材料、功率电子器件及电源模块要津本事商榷”之课题“Si 衬底上 GaN 基功率电子器件的可靠性升迁本事及功率集成本事商榷”,课题牵头东谈主,390.6万,进行中。

近期代表性学术论文(*为通信作家):

1)  T. Zhang, Y. Lv, R. Li, Y. Zhang, Y. Zhang, X. Li*, J. Zhang*, and Y. Hao, “Current-Collapse Suppression of High-Performance Lateral AlGaN/GaN Schottky Barrier Diodes by a Thick GaN Cap Layer,” IEEE Electron Device Lett., vol. 42, no. 4, pp. 477–480, Apr. 2021.

2)  T. Zhang, Y. Zhang, J. Zhang*, X. Li*, Y. Lv, and Y. Hao, “Current Transport Mechanism of High-Performance Novel GaN MIS Diode,” IEEE Electron Device Lett., vol. 42, no. 3, pp. 304–307, Mar. 2021.

3)  X. Li*, M. Van Hove, M. Zhao, K. Geens, V.-P. Lempinen, J. Sormunen, G. Groeseneken, and S. Decoutere, “200 V Enhancement-mode p-GaN HEMTs Fabricated on 200 mm GaN-on-SOI with Trench Isolation for Monolithic Integration,” IEEE Electron Device Lett., vol. 38, no. 7, pp. 918–921, Jul. 2017.

4)  X. Li*, M. Van Hove, M. Zhao, B. Bakeroot, S. You, G. Groeseneken, and S. Decoutere, “Investigation on Carrier Transport through AlN Nucleation Layer from Differently Doped Si(111) Substrates,” IEEE Trans. Electron Devices, vol. 65, no. 5, pp. 1721–1727, May 2018.

5)  X. Li*, M. Van Hove, M. Zhao, K. Geens, W. Guo, S. You, S. Stoffels, V.-P. Lempinen, J. Sormunen, G. Groeseneken, and S. Decoutere, “Suppression of the backgating effect of enhancement-mode p-GaN HEMTs on 200-mm GaN-on-SOI for monolithic integration,” IEEE Electron Device Lett., vol. 39, no. 7, pp. 999–1002, Jul. 2018

6)  X. Li*, M. Zhao, B. Bakeroot, K. Geens, W. Guo, S. You, S. Stoffels, V.-P. Lempinen, J. Sormunen, G. Groeseneken, and S. Decoutere, “Buffer vertical leakage mechanism and reliability of 200-mm GaN-on-SOI,” IEEE Trans. Electron Devices, vol. 66, no. 1, pp. 553–560, Jan. 2019.

7)  X. Li*, K. Geens, W. Guo, S. You, M. Zhao, D. Fahle, V. Odnoblyudov, G. Groeseneken, and S. Decoutere, “Demonstration of GaN integrated half-bridge with on-chip drivers on 200-mm engineered substrates,” IEEE Electron Device Lett., vol. 40, no. 9, pp. 1499–1502, Sep. 2019.

8)  X.Li*, B. Bakeroot, Z. Wu, N. Amirifar, S. You, N. Posthuma, M. Zhao, H. Liang, G. Groeseneken, and S. Decoutere, “Observation of Dynamic VTH of p-GaN Gate HEMTs by Fast Sweeping Characterization,” IEEE Electron Device Lett., vol. 41, no. 4, pp. 577–580, Apr. 2020.

9)  X. Li*, K. Geens, D. Wellekens, M. Zhao, A. Magnani, N. Amirifar, B. Bakeroot, S. You, D. Fahle, H. Hahn, M. Heuken, V. Odnoblyudov, O. Aktas, C. Basceri, D. Marcon, G. Groeseneken, and S. Decoutere, “Integration of 650 V GaN Power ICs on 200 mm Engineered Substrates,” IEEE Transactions on Semiconductor Manufacturing, vol. 33, no. 4, pp. 534–538, Nov. 2020.

10) X. Li*, N. Posthuma, B. Bakeroot, H. Liang, S. You, Z. Wu, M. Zhao, G. Groeseneken, and S. Decoutere, “Investigating the Current Collapse Mechanisms of p-GaN Gate HEMTs by Different Passivation Dielectrics,” IEEE Trans. Power Electron., vol. 36, no. 5, pp. 4927–4930, May 2021.

11) D. Cingu, X. Li*, B. Bakeroot, N. Amirifar, K. Geens, M. Zhao, S. You, G. Groeseneken, and S. Decoutere, “Reliability of p-GaN gate HEMTs in Reverse Conduction,” IEEE Trans. on Electron Devices, vol. 68, no. 2, pp. 645–652, Feb. 2021.

12) S. You, X. Li*, K. Geens, N. Posthuma, M. Zhao, H. Liang, G. Groeseneken, and S. Decoutere, “GaN power ICs Design Using the MIT Virtual Source GaNFET Compact Model with Gate Leakage and VT Instability Effect,” Semiconductor Science and Technology, vol. 36, no. 3, pp. 035008, Mar. 2021.

13) M. Borga*, C. De Santi, S. Stoffels, B. Bakeroot, X. Li, M. Zhao, M. Van Hove, S. Decoutere, G. Meneghesso, M. Meneghini, and E. Zanoni, “Modeling of the Vertical Leakage Current in AlN/Si Heterojunctions for GaN Power Applications,” IEEE Trans. on Electron Devices, vol. 67, no. 2, pp. 595–599, Feb. 2020.

14) M. Borga*, M. Meneghini, S. Stoffels, M. Van Hove, M. Zhao, X. Li, S. Decoutere, E. Zanoni, and G. Meneghesso, “Impact of the substrate and buffer design on the performance of GaN on Si power HEMTs,” Microelectronics Reliability, vol. 88, pp. 584–588, Sep. 2018.

15) M. Borga*, M. Meneghini, S. Stoffels, X. Li, N. Posthuma, M. Van Hove, S. Decoutere, G. Meneghesso, and E. Zanoni, “Impact of Substrate Resistivity on the Vertical Leakage, Breakdown, and Trapping in GaN-on-Si E-Mode HEMTs,” IEEE Trans. on Electron Devices, vol. 65, no. 7, pp. 2765–2770, Jul. 2018.

近期代表性会论说文:

1)    X. Li*, N. Amirifar, K. Geens, M. Zhao, W. Guo, H. Liang, S. You, N. Posthuma, B. De Jaeger, S. Stoffels, B. Bakeroot, D. Wellekens, B. Vanhove, T. Cosnier, R. Langer, D. Marcon, G. Groeseneken, and S. Decoutere, “GaN-on-SOI: Monolithically Integrated All-GaN ICs for Power Conversion,” in IEDM Tech. Dig., pp.4.4.1–4.4.4, Dec. 7–11, 2019.

2)    X. Li*, K. Geens, W. Guo, M. Zhao, S. You, N. Posthuma, S. Stoffels, H. Liang, V. Odnoblyudov, C. Basceri, O. Aktas, G. Groeseneken, and S. Decoutere, “  p-GaN gate HEMTs, RTL logic, and gate driver monolithically integrated on 200 mm QST® substrates for GaN ICs,” in 13th International Conference on Nitride Semiconductors 2019 (ICNS), Jul. 7–12, 2019.    

3)    X. Li*, M. Zhao, K. Geens, W. Guo, S You, S. Stoffels, G. Groeseneken, and S. Decoutere, “Monolithic integration of half-bridge on GaN-on-SOI ,” in International Workshop on Nitride Semiconductors (IWN), Nov. 11–16, 2018.

萝莉 幻塔

4)    X. Li*, M. Van Hove, M. Zhao, K. Geens, V. Lempinen, J. Sormunen, S. Stoffels, G. Groeseneken, and S. Decoutere, “200 V enhancement-mode p-GaN HEMTs fabricated on 200 mm GaN-on-SOI with trench isolation for monolithic integration,” in 41th Workshop on Compound Semiconductor Devices and Integrated Circuits  (WOCSDICE), pp. 103–104, May 21–24, 2017.